Implantable stimulation devices generate and deliver electrical stimuli to body nerves and tissues for the therapy of various biological disorders, such as pacemakers to treat cardiac arrhythmia, defibrillators to treat cardiac fibrillation, cochlear stimulators to treat deafness, retinal stimulators to treat blindness, muscle stimulators to produce coordinated limb movement, spinal cord stimulators to treat chronic pain, cortical and deep brain stimulators to treat motor and psychological disorders, and other neural stimulators to treat urinary incontinence, sleep apnea, shoulder sublaxation, etc. The description that follows will generally focus on the use of the invention within a Spinal Cord Stimulation (SCS) system, such as that disclosed in U.S. Pat. No. 6,516,227. However, the present invention may find applicability in any implantable stimulator.
As shown in FIGS. 1A-1C, a SCS system typically includes an Implantable Pulse Generator (IPG) 100, which includes a biocompatible device case 30 formed of a conductive material such as titanium for example. The case 30 typically holds the circuitry and battery 26 necessary for the IPG to function, although IPGs can also be powered via external RF energy and without a battery. The IPG 100 is coupled to electrodes 106 via one or more electrode leads (two such leads 102 and 104 are shown), such that the electrodes 106 form an electrode array 110. The electrodes 106 are carried on a flexible body 108, which also houses the individual signal wires 112 and 114 coupled to each electrode. In the illustrated embodiment, there are eight electrodes on lead 102, labeled E1-E8, and eight electrodes on lead 104, labeled E9-E16, although the number of leads and electrodes is application specific and therefore can vary. The leads 102, 104 couple to the IPG 100 using lead connectors 38a and 38b, which are fixed in a non-conductive header material 36, which can comprise an epoxy for example.
As shown in the cross-section of FIG. 1C, the IPG 100 typically includes an electronic substrate assembly including a printed circuit board (PCB) 16, along with various electronic components 20 mounted to the PCB 16, some of which are discussed subsequently. Two coils (more generally, antennas) are generally present in the IPG 100: a telemetry coil 13 used to transmit/receive data to/from an external controller, and a charging coil 18 for charging or recharging the IPG's battery 26 using an external charger. In this example, the telemetry coil 13 and charging coil 18 are within the case 30, as disclosed in U.S. Patent Publication 2011/0112610. (FIG. 1B shows the IPG 100 with the case 30 removed to ease the viewing of the two coils 13 and 18). However, the telemetry coil 13 may also be mounted within the header 36 of the IPG 100 (not shown).
FIGS. 2A and 2B show different current distribution architectures for forming pulses at the electrodes in an IPG 100. FIG. 2A shows an architecture in which each electrode is provided with a dedicated current source (PDAC 50) and current sink (NDAC 60), such as is disclosed in U.S. Pat. No. 6,181,969 for example. The PDAC 50 and NDAC 60 are so named because the amplitude of the analog current they source or sink is digitally controllable (hence, they are Digital-to-Analog Converters, or DACs), and because they are typically made from P-channel and N-channel transistors respectively. As described in U.S. Pat. No. 7,444,181, which is incorporated by reference in its entirety, the PDACs and NDACs can comprise current mirrors, each of which contains at least one output transistor(s) coupled in parallel to set the desired current.
The architecture of FIG. 2A can be used to pass current between any of the N electrodes. For example, and as illustrated, PDAC 50-1 has been programmed to source a constant stimulation current of Iout, while NDAC 60-2 has been enabled to sink a constant current also equal to Iout. The other PDACs and NDACs are disabled in this example. This results in Iout passing out of electrode E1, through the patient's tissue (not shown), and returning back through electrode E2. More than one PDAC 50 or NDAC 60 can enabled at one time to provide more complicated currents in the patient's tissue. As one skilled in the art understands, stimulation currents are typically issued in the form of pulses, which may be uniphasic or biphasic. Any of the electrodes E1-EN can be chosen to either source or sink current.
FIG. 2B shows a distributed architecture in which sourced or sunk current are passed to or from the electrodes using switch matrices 70P and 70N, such as is disclosed in U.S. Patent Publication 2007/0038250 for example. Switching matrix 70P is controllable to source current from any of the PDACs 50 to any of the electrodes, while switching matrix 70N is controllable to sink current from any of the electrodes via NDACs 60. In the example shown, which also involves sending a stimulation current of Iout from E1 to E2, switching matrix 70P has coupled PDAC 50-2 to E1, while switching matrix 70N has coupled NDAC 60-1 to E2. The switching matrices can also be used to send sourced or sunk current to more than one electrode, and the sourced or sunk current from multiple PDACs 50 or NDACs 60 can be sent to the same electrode. Some distributed architectures may only employ a single PDAC 50 and NDAC 60.
Both of the architectures employ decoupling capacitors C1-CN coupled to each of the electrodes. As is well known, decoupling capacitors C1-CN acts as a safety measure to prevent direct DC current injection into the patient.
Regardless of the architecture used, it is important to set the compliance voltage V+ to appropriate levels. The compliance voltage V+ comprises the power supply voltage used by the DAC circuitry that issues the pulses. V+ is generated by boosting the battery voltage, Vbat, and it is desired that V+ be set to an optimal level for the current that the DACs must provide: if too low, the electrodes will not be able to issue pulses of the desired amplitudes; if too high, battery power is unnecessarily wasted.
One approach to setting V+ is disclosed in U.S. Pat. No. 7,444,181, which is summarized here in FIGS. 3 and 4. In the '181 patent, the voltage drops across the active PDACs (Vp1, Vp2, etc.) and NDACs (Vn1, Vn2, etc.) are measured and used to set V+. This occurs by selecting a tap connected to one of the active DACs using a switching matrix 75. The voltage on the selected tap is sent to an Analog-to-Digital (A/D) converter 80, and the digitized value is sent to and stored in control circuitry 85 (e.g., a microcontroller). Because the control circuitry 85 knows a priori the voltage on the other sides of the DACs (V+ for the PDACs, and ground for the NDACs), the voltage drops Vp and Vn can be determined using the digitized tap values.
Operating within the control circuitry 85 is a V+ algorithm 90, which assesses the voltage drops across the active PDACs and NDACs, and sends a control signal to a V+ regulator 95 to set an appropriate value for V+. Generally speaking, the algorithm seeks to bring the voltage drops across the active PDACs (Vp) and NDACs (Vn) within appropriate ranges. These ranges are based on the architectures used for the PDACs and NDACs, which as noted earlier comprise current mirrors which use output transistor(s) to drive the currents. As explained in the '181 patent, it is desired that the output transistor(s) operate in a saturation mode, such that the channels of the transistors are in “pinch off.” Keeping the output transistor(s) in saturation requires that the drain-to-source voltage drop across the output transistor(s), Vds (i.e., Vp and Vn), be greater that the gate-to-source voltage (Vgs) minus their threshold voltage (Vt). Operation in saturation is desired for providing the proper amount of current: if Vds is too low and the output transistor(s) are operating in sub-saturation, the DACs will not be able to provide the desired current. However, it is also desired that Vds not be too high, because unnecessary additional voltage drop across the output transistor(s) merely wastes power, which is highly undesirable in the battery-operated IPG 100. Due to the differences inherent in the P-channel and N-channel transistors used in the PDACs and NDACs, the desired ranges for Vp and Vn disclosed in the '181 patent are different: e.g., 1.5 to 2.1V for Vp, and 1.2 to 1.8V for Vn. Essentially, the V+ algorithm 90 tries to adjust V+ until Vp and Vn for all the active DACs are within these ranges if possible. (It may not be possible for all of the active DACs to be within these ranges given possible differences in the currents used and difference in tissue resistance between the electrodes).
The V+ algorithm 90 of the '181 patent is described further in FIG. 4. Normally, the algorithm 90 would start with the compliance voltage, V+ at its maximum value (e.g., V+(max)=18V), and as it operates it gradually reduces V+ to a desired level. The algorithm starts by first acquiring the voltage drops for the active NDACs (Vn1, Vn2, etc.), which measurements are preferably made toward the end of the pulses. Next, a minimum of these voltages (Min(Vn)) is determined. This minimum voltage would suggest the NDAC most at risk to be in sub-saturation, and hence in this embodiment of the algorithm is considered the most efficient to track. Accordingly, the algorithm 90 next asks how that minimum value compares relative to the range of guard band voltages for the NDACs. Essentially, if Min(Vn) is higher than the maximum guard band voltage for the NDACs (e.g., 1.8V), the compliance voltage V+ is decreased, because it can be inferred that all NDACs are at this point operating with voltage drops that are too high to be optimal from a power consumption standpoint. To expedite the iterative nature of the algorithm, the extent to which the compliance voltage V+ is decreased scales with the extent to which Min(Vn) exceeds the upper guard band voltage for the NDACs. Thus, if Min(Vn) is very high above the guard band, the compliance voltage is decreased by a large amount, but if barely above the guard band the compliance voltage is decreased by a small amount.
As the compliance voltage V+ is adjusted, Min(Vn) will eventually come within the guard band range (e.g., between 1.2V and 1.8V), and the PDACs can then be assessed. The algorithm 90 then measures the voltage drops for the active PDACs (Vp1, Vp2, etc.). Next, a minimum of these voltages (Min(Vp)) is determined, and the algorithm 90 then proceeds as described earlier for the NDACs by adjusting V+ until the Min(Vp) is brought within its guard band range (e.g., between 1.5V and 2.1V). At this point, V+ is now set for the IPG at value V+(opt).
FIG. 5 further illustrates the operation of V+ algorithm 90, and assumes for simplicity that only one PDAC and one NDAC are operating to provide constant current pulses at electrodes E1 and E2, and thus each measured Vn or Vp comprises the minimum for purposes of the algorithm 90. As shown, the compliance voltage V+ starts at a maximum value (V+(max)). Then Vn is measured at the end of the pulse across the active NDAC that is sinking current from electrode E2. If Vn is higher than its guard band range, the V+ algorithm reduces V+, and Vn is then measured on a subsequent pulse. Eventually as V+ falls, Vn is brought within its guard band, and the V+ algorithm 90 can start monitoring Vp at the end of the pulses for the active PDAC that is sourcing current to electrode E1. If Vp is higher than its guard band range, the V+ algorithm reduces V+, and Vp is again measured on a subsequent pulse. Eventually Vp is brought within its guard band, at which point V+ determines that the current value for V+ is optimal, and thus V+ is set by algorithm 90 to that optimal value, V+(opt).